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| HT9580 character pager controller 1 april 28, 2000 preliminary features operating voltage: 2.4v~3.5v temperature range: -30 cto+85 c low power, high performance m6502 core low power crystal oscillator control 512/1200/2400 bps data rate operation ccir radio paging code no.1 (pocsag) compatible 76.8khz crystal for all available data rates high/low system clock switching capability 44 kbytes program rom 848 bytes global data ram internal 2 mbits character rom 256 kbits internal sram external option up to 2 mbits character rom or 2 mbits sram sed15x(ksx), mc141x and hd66410 series lcd driver compatible interface option 46 bytes message buffer one 16-bit timer and one 8-bit timer internal 2hz or 1hz rtc or real time clock option single buzzer generator output (bz) with duty cycle control low current halt mode operation 16-bit watchdog timer built-in data filter (16-times over-sampling ) and bit clock recovery advanced synchronization algorithm 2-bit random and (optional) 4-bit burst er - ror correction for address and message up to 6 user addresses and 6 user frames, independently programmable 3 rf power-on timing control pins and received data inversion (optional) built in spi circuit out-of-range condition indicator one internal 8-bit d/a converter battery fail and battery low detection 80-pin lqfp package general description the HT9580 is a high performance pager con- troller which can be used for chinese pager system applications. the HT9580 4-in-1 char- acter pager controller combines a pocsag de- coder with a m6502 microprocessor core, 2 mbits character rom and 256 kbits sram to provide both high decoder performance and ex- cellent system flexibility. the decoder utilizes a 2-bit random error correction algorithm and therefore provides excellent decoder sensitiv- ity. the controller contains a full function pager decoder at a 512, 1200, 2400 bps data rates. using an m6502 core takes advantage of a flexible external control interface, lcd driver chips and abundant programming resources from worldwide providers. the internal spi would communicate with spi of flex tm high speed pager decoder. flex tm is a trademark of motorola inc.
block diagram HT9580 2 april 28, 2000 preliminary !"#$% &' ! (#$% ) * + , ( " - . ) * + , $ /$!% & 01 /$ 2 01 /$ ' 3 3 - 43 5 ! % 3 3 66 4 $ 3 3 /$ 7 8 9 $ 34 /$ 3 $ 0 34 /$ $ $/ 2 2 - !9 &% - )!9 &% 9 8: ) * + , ( /$ /$ $ $ 9 - ) ! % 9) /0 ;" $$ ; $$ 00 0 + , ( $< 6 = = : = = = = , 7 > $/$ ? $ - 0 0 ? @ & 00 0 6$/3$ 0 9 343 5 < 3 8 )8a *8 9 8 9 82 ' ') / 9 5 9 : 3 ( , + * ) "b#$ 8 ? =9& b &' ' &' ' $ 3$ = 9 pin assignment HT9580 3 april 28, 2000 preliminary ) + ( ( " ) + =9& ? 28 > ( , + * ) ) 8 9 *8 9 )8a 8 , + * ) 9) 9 ') ' = = = = = : = ( , + * ) 8: = a= 9 * + , ( " . ) * + , = 9 + , ( pin description pin no. pin name i/o description 1, 25, 56 vdd positive power supply 2 lcd_cs1 o lcd driver chip select control (for slave lcd driver) 3 lcd_cs0 o lcd driver chip select control (for master lcd driver) 4 lcd_cl o lcd driver clock output 5 lcd_a0 o lcd driver data/command select control 6 lcd_rw o lcd driver read/write signal output 7 lcd_e o lcd driver enable clock control 15~8 d0~d7 i/o 8-bit, tristate, bidirectional i/o data bus. 16 r/w o read/write signal output 17 sram_ce o sram chip enable. this signal is generated from the HT9580 to provide read or write timing for external sram devices. (see ap - plication circuit) 18 mask_ce o mask rom chip enable. this signal is generated from the HT9580 to provide read timing for external mask rom devices. (see application circuit) 19 oe o mask rom or sram output enable. this signal is generated from the HT9580 to provide read timing for external mask rom and sram devices. (see application circuit) 20 psen o program store enable. this pin is used to connect the oe and ce pins of the external 44 kbytes program rom when the mode_p internal pad is connected to vss. (see note) 21~24 ra17~ra14 o extended address bus pins 26 p_mode i internal or external program rom selection without pull-high re- sistor. if the pin connects to vdd, the internal program rom will be fetched (normal type), otherwise the external program rom will be fetched when the pin connects to vss (romless). 27, 57, 78 vss negative power supply 43~28 a0~a15 o address bus pins. this is used for memory and i/o exchanges on the data bus. 44 tmr1 i schmitt trigger input for timer1 counter with pull-high resisor. 45~52 pb0~pb7 i/o general input/output port b. the input cell structures can be se - lected as cmos or cmos with pull-high resistors. 53~54 pc0~pc1 i/o general input/output port c. the input cell structures can be se - lected as cmos or cmos with pull-high resistors. 55 bz o buzzer non-inverting bz output HT9580 4 april 28, 2000 preliminary pin no. pin name i/o description 58 bal i battery voltage detector input with pull-high resistor. srdy i spi slave ready this slave ready pin is a schmitt trigger input with pull-high resistor. when the slave initiates the spi transfer, a high to low transition activates an interrupt. when the master initiates the spi transfer, a high to low transition trigger the master to start the transfer. 59 baf i battery fail indication input, active low. 60 da_out o d/a converter output. this pin is an 8-bit d/a analog output 61 rssi i rssi output from if circuit. this pin should be pulled high or low externally when this pin is not used. 62 di i pocsag code input serial data. cmos input with pull-high re - sistor. miso i spi master-in-slave-out this is the data input with pull-high resistor for spi communications. 63 bs3 o pll power control enable, cmos output mosi o spi master-out-slave-in this is the data output for spi commu - nications. 64 bs2 o rf quick charge control enable, cmos output sck i/o spi serial clock the sck signal is used to synchronize the data transfer. if HT9580 is in the master mode, the sck is output clock. otherwise, sck is input clock if HT9580 is in the slave mode. 65 bs1 o pager receiver power control enable output, cmos output ss o spi slave select this signal is used to enable the spi slave for transfer. 66 ts i decoder test mode input pin, active low with pull-high resistor. 72~67 pa0~pa5 i/o general input/output port a. these ports can be programmed to have a wake-up capability for applications in keyboard operations or as normal i/o. also the input cell structures are all schmitt trigger types and can be selected between cmos or cmos with pull-high resistors. 73 reset i schmitt trigger reset input, active low. 74 tsc i c test mode input pin, active low with internal pull-high resis - tor. the test circuit will be activated when this pin pulls low. 75 ts1 i decoder test mode input pin, active low with pull-high resistor. the internal test mode will be activated when this pin pulls low. 77 76 osc1 osc2 i o osc1 and osc2 are connected to an rc network to form a main clock oscillator 80 79 x1 x2 i o x1 and x2 are connected to a crystal to form an internal low power clock oscillator (32.768khz, 76.8khz, or 153.6khz) HT9580 5 april 28, 2000 preliminary absolute maximum ratings supply voltage.............................. 0.3v to 3.6v storage temperature................. 55 cto150 c input voltage .................v ss 0.5v to v dd +0.5v operating temperature .............. 30 cto85 c current drain per pin excluding v dd and v ss ............................................................................10ma note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this de - vice at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 3v application 2.4 3.0 3.5 v i dd operating current 3v no load, osc1=1mhz f x1 =76.8khz 300 a i stp halt mode current 3v no load, c clock stop, f x1 =76.8khz 100 a v il input low voltage for i/o port 3v 0 0.3 v dd v v ih input high voltage for i/o port 3v 0.7 v dd 3v v il1 input low voltage 3v 0 0.3 v dd v v ih1 input high voltage 3v 0.7 v dd 3v v il2 input low voltage (baf )3v 0 0.9 v v ih2 input high voltage (baf )3v 1.0 3v v ol output low voltage 3v 0.4 v v oh output high voltage 3v 2.3 v i ol i/o port sink current 3v v ol =0.3v 2.0 3.6 ma i oh i/o port source current 3v v oh =2.7v 1.2 2.2 ma i ol1 bz, pc0~pc1 sink current 3v v ol =0.3v 2 4.5 ma i oh1 bz, pc0~pc1 source current 3v v oh =2.7v 1.5 2.5 ma i ol2 bs1, bs2, bs3 sink current 3v v ol =0.3v 350 a i oh2 bs1, bs2, bs3 source current 3v v oh =2.7v 1.0 ma r osc rc oscillator resistor 3v f osc =1mhz 51 k r ph i/o port pull-high resistance 3v 100 250 k HT9580 6 april 28, 2000 preliminary a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f osc1 main clock (rc osc) 3v 76.8 1000 2000 khz d osc1 main clock duty cycle 3v 40 50 60 % f x1 pager clock input (crystal osc) 3v 32.768 76.8 153.6 khz t reset reset input pulse width 1 ms functional description memory map HT9580 7 april 28, 2000 preliminary 89 0 4 ( / 366 +( 7 # **( +" 7 # , ) - * - + - ( - " - ?- - ??- ) - *??- 8 1 5 9 "a # 8 1 "a # / 9 4 )"a / 9 4 (* " b b- b b- b b- - )???- * - +???- , - ???- - ???- ??? - ??? - ??? - ???- ????- 5 9 4 ! % "a # - )???- * !) #$% 1 5 9 4 ! % "a # - )???- * !) #$% 4 ! % "a # * - +???- *!*)a % 1 4 ! % "a # * - +???- * !),(a % HT9580 memory mapping table (i/o and data space) address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0000h config. halt clk_sel osc_mod lpm rtc bz_clk mdut mgen 0001 0000 0001h wdt-tmr x x tmr0_pr1 tmr0_pr0 wdten ws2 ws1 ws0 0000 0111 0002h clr wdt x x x x x x x x uuuu uuuu 0003h bz-l bzl7 bzl6 bzl5 bzl4 bzl3 bzl2 bzl1 bzl0 0000 0000 0004h bz-h bzh7 bzh6 bzh5 bzh4 bzh3 bzh2 bzh1 bzh0 0000 0000 0005h int ctrl 0 0 0 rtcen ormsk rtcmsk tm1imsk tm0imsk 0000 1111 0006h int flag 0 rtc_fg dr_fg bf_fg wdtovfg or_fg tm1ovfg tm0ovfg 0000 0000 0007h tmrc tmr1mod x tmr1clk tmr0clk tmr1edg tmr0edg tmr1en tmr0en 0000 0000 0008h tmr1l tm1d7 tm1d6 tm1d5 tm1d4 tm1d3 tm1d2 tm1d1 tm1d0 uuuu uuuu 0009h tmr1h tm1d15 tm1d14 tm1d13 tm1d12 tm1d11 tm1d10 tm1d9 tm1d8 uuuu uuuu 000ah tmr0 tm0d7 tm0d6 tm0d5 tm0d4 tm0d3 tm0d2 tm0d1 tm0d0 uuuu uuuu 000bh pa data x x pa5 pa4 pa3 pa2 pa1 pa0 uu11 1111 000ch pb data pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 1111 1111 000dh pc data x x x x x x pc1 pc0 uuuu uu11 000eh pac x x pac5 pac4 pac3 pac2 pac1 pac0 uu11 1111 000fh pbc pbc7 pbc6 pbc5 pbc4 pbc3 pbc3 pbc1 pbc0 1111 1111 0010h pcc x x x x x x pcc1 pcc0 uuuu uu11 0011h pa wue x x pawue5 pawue4 pawue3 pawue2 pawue1 pawue0 uu00 0000 0012h pa im x x paim5 paim4 paim3 paim2 paim1 paim0 uu11 1111 0013h pb im pbim7 pbim6 pbim5 pbim4 pbim3 pbim2 pbim1 pbim0 1111 1111 0014h pc im x x x x x x pcim1 pcim0 uuuu uu11 0015h mrom-bp bp_modm1 bp_modm0 m_bp5 m_bp4 m_bp3 m_bp2 m_bp1 m_bp0 0000 0000 0016h sram-bp bp_mods1 bp_mods0 s_bp5 s_bp4 s_bp3 s_bp2 s_bp1 s_bp0 0000 0000 0017h lcd_ctrl lcd-chip1 lcd-chip0 lcd-clk clk-mod lcd-cs1 lcd-cs0 lcd-a0 lcd-wrb 0000 1101 0018h lcd_cmd lcd_d7 lcd_d6 lcd_d5 lcd_d4 lcd_d3 lcd_d2 lcd_d1 lcd_d0 uuuu uuuu 0019h decoder control/ flag xbl or x stb x res on uu0u uu01 001ah~ 002eh decoder configuration memory uuuu uuuu 002fh d/a-l da7 da6 da5 da4 da3 da2 da1 da0 0000 0000 0030h d/a-h x x x x x d/a_pd rssi bat uuuu u1uu 0031h buffer status msg_end x count_5 count_4 count_3 count_2 count_1 count_0 0uuu uuuu 0032h spi-config s/m len1 len0 reqst spifg clk_edg spi_en start 0111 1000 0033h spi-speed sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0000 0000 0034h spi-out3 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0035h spi-out2 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0036h spi-out1 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0037h spi-out0 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0038h spi-in3 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0039h spi-in2 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 003ah spi-in1 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 003bh spi-in0 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 HT9580 8 april 28, 2000 preliminary HT9580 memory attribute table (i/o and data space) address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0000h config. r/w r/w r/w r/w r/w r/w r/w r/w 0001 0000 0001h wdt-tmr x x r/w r/w r/w r/w r/w r/w 0000 0111 0002h clr wdt w w w w w w w w uuuu uuuu 0003h bz-l r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0004h bz-h r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0005h int ctrl 0 0 0 r/w r/w r/w r/w r/w 0000 1111 0006h int flag 0 r/w r/w r r/w r/w r/w r/w 0000 0000 0007h tmrc r/w x r/w r/w r/w r/w r/w r/w 0000 0000 0008h tmr1l r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 0009h tmr1h r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 000ah tmr0 r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 000bh pa data x x r/w r/w r/w r/w r/w r/w uuuu uuuu 000ch pb data r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 000dh pc data x x x x x x r/w r/w uuuu uuuu 000eh pac x x r/w r/w r/w r/w r/w r/w uu11 1111 000fh pbc r/w r/w r/w r/w r/w r/w r/w r/w 1111 1111 0010h pcc x x x x x x r/w r/w uuuu uu11 0011h pa wue x x r/w r/w r/w r/w r/w r/w uu00 0000 0012h pa im x x r/w r/w r/w r/w r/w r/w uu00 0000 0013h pb im r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0014h pc im x x x x x x r/w r/w uuuu uu00 0015h mrom-bp r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0016h sram-bp r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0017h lcd_ctrl r/w r/w r/w r/w r/w r/w r/w r/w 0000 1101 0018h lcd_cmd r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 0019h decoder control/ flag x r/w r x r x r/w r/w uu0u uu01 001ah~ 002eh decoder configuration memory r/w r/w r/w r/w r/w r/w r/w r/w uuuu uuuu 002fh d/a-l r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0030h d/a-h x x x x x r/w r r uuuu u1uu 0031h buffer status r x r r r r r r 0uuu uuuu 0032h spi-config r/w r/w r/w r r r/w r/w r/w 0111 1000 0033h spi-speed r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0034h spi-out3 r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0035h spi-out2 r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0036h spi-out1 r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0037h spi-out0 r/w r/w r/w r/w r/w r/w r/w r/w 0000 0000 0038h spi-in3 r r r r r r r r 0000 0000 0039h spi-in2 r r r r r r r r 0000 0000 003ah spi-in1 r r r r r r r r 0000 0000 003bh spi-in0 r r r r r r r r 0000 0000 note: r read only w write only r/w read or write x n/a HT9580 9 april 28, 2000y preliminary configuration register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0000h config. halt clk_sel osc_mod lpm rtc bz_clk mdut mgen 0001 0000 HT9580 10 april 28, 2000 preliminary oscillator configuration there are two clock source input pins on the chip, the main clock and the pager decoder in - put clock. the main clock is generated by an rc network. the system clock may be the osc in - put or the x1-clock depending on bit clk_sel . the pager decoder input clock co - mes from two external pins, x1 and x2. the fre - quency of the sub-clock will be double that of the x1, x2 input clock. the osc1 main clock will be generated from an rc network that needs an external resistor (see application cir - cuit). the system clock may be x1-clock, df or rc clock. if no higher frequency (rc) is needed, the external resistor between osc1 and osc2 can be removed. the system clock can be switched by bit clk_sel .if clk_sel =0 (por state), the system clock will be x1-clock. in other cases, with clk_sel =1, the osc in - put clock will be the system clock. the clock switching function will assist software pro- grammers to change the c system clock with- in an adequate time if necessary. the osc_mod bit selects the osc input clock to be either rc or df. if osc_mod is set to low then the rc configuration is selected, oth - erwise the df application is selected. the pro - grammer should note that the condition of clk_sel , halt and osc_mod assures that the system clock is working properly. it is recommended that the osc clock source is ei - ther df or rc. if df and rc are necessary, it is required to switch the system clock to x1-clock before switching between df and rc. then switch the system clock back to the osc input by using bit clk_sel if the switching action of df and rc is complete. before enter halt mode, the system clock must select x1-clock. the HT9580 will generate two rtc frequen - cies, 1hz and 2hz respectively, determined by bit rtc. if the bit is logic low, the 1hz rtc fre - quency will be selected, otherwise the 2hz rtc frequency will be selected. the rtc counter is enabled/disabled by bit rtcen and can be masked or not masked as determined by the bit rtcmsk of the interrupt control register 9 ' b 9=9 9 c c ? - a= c' b c9 43 ?d3 3# b#$ $44 3 ' $ ' b 9 43 ? 3#b ' b 3 - ef $ 9 3 )- ef $ 9 3 $ 93 rtc block diagram HT9580 11 april 28, 2000 preliminary (0005h). if the rtc counter is enabled, the rtc counter will start to count. the rtc coun - ter source clock is the x1-clock, so the x1 clock setting via by spf12, spf13 and spf14 should be correct. in order to guarantee that the system clock has started and stabilized, the sst (system start-up timer) provides an extra delay of 1024 system clock pulse when the system is powered up. 10 rtc select 2hz as the rtc select 1hz as the rtc the low power oscillator of the pager decoder input clock should be crystal type. the decoder subsystem low power oscillator, on the other hand, is of a crystal type which is designed with a power on start-up function to reduce the sta - bilization time of the oscillator. this start-up function is enabled by bit lpm which is ini - tially set high at power on reset, and should be cleared to low so as to enable the low-power os - cillator function. the oscillator configuration is running in the low power mode. the system clock oscillator can be enabled/dis - abled by the register bit, halt . the system clock circuit is powered down, when the bit is set to high. on the other hand, the system clock circuit is powered up, when the bit is low. when this bit is set high, the cpu is also stopped. when this bit is cleared low, the cpu core re - turns to its normal operation. after this is set high by the software, it may also be cleared low when reset, interrupt (irq or nmi ), rtc timeout, and port wake-up conditions are met. 01 halt system clock enable system clock powered down the wdt is a 16-bit counter and sourced by the ' ') @ 4 @ $ 63 $ ! @ 4 @ 0 % , , low power oscillator sub-clock divided by 8. the counter is seg - mented as a 9-bit prescaler and a 7-bit user pro - grammable counter. the input clock is first divided by 512 (9-stage) to get the nominal time-out period. the output of the 9-bit pre-scaler can then be divided by a 7-bit pro - grammable counter to generate the longer watchdog time-out depending on the user sre - quirements. the 7-bit programmable counter is controlled by 3 register bits, ws0~2. the watchdog timer is enabled/disabled by a control bit wdten. to prevent the overflow of this watchdog timer, a clear-wdt operation should be executed before the timer overflows. the clear-wdt operation is to write any number to the register, clrwdt (0002h). when the watchdog timer overflows (checked by bit 3 of 0006h wdtovfg ), the program counter is set to fffc h and fffd h to read the program start vector. the definitions of the control bits are listed below. 10 wdten enable the watchdog timer disable the watchdog timer wdt-tmr (watchdog timer) register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0001h wdt-tmr x x tmr0_pr1 tmr0_pr0 wdten ws2 ws1 ws0 0000 0011 0002h clr wdt xxxxxxxx uuuu uuuu HT9580 12 april 28, 2000 preliminary the wdt 7-bit counter is programmed by bits ws0~ws2. the division ratio for the counter is listed in the table. ws2 ws1 ws0 division ratio 0001:1 0011:2 0101:4 0111:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 the other pair tmr0_pr0 and tmr0_pr1 are used to select the prescaler ratio for timer0. the definition is shown in the table. tmr0_pr1 tmr0_pr0 tmr0 prescaler ratio 0 0 1/4 0 1 1/8 1 0 1/16 1 1 1/32 buzzer generator registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0003h bz-l bzl7 bzl6 bzl5 bzl4 bzl3 bzl2 bzl1 bzl0 0000 0000 0004h bz-h bzh7 bzh6 bzh5 bzh4 bzh3 bzh2 bzh1 bzh0 0000 0000 the buzzer generator is composed of a 16-bit pfd counter and a duty cycle control. the coun- ter value is set by two registers, namely bz-h and bz-l. the source for this generator may be the system clock or the x1-clock. the buzzer generator is enabled/disabled by the register bit mgen in the configuration regis - ter(0000h). when this bit is set high, the buzzer generator is activated. there is another bit in the configuration register(0000h) which controls the buzzer output volume, bit mdut . if the bit is logic high, the output of the bz will be modulated by the x1-clock. the clock source of the buzzer is selected by bit bz_clk . when bz_clk=0, the clock source is the system clock. on the other hand, when bz_clk=1, the value of the selector will be the x1-clock. the truth table for enabling/disabling the buzzer generator is shown in the table. 10 mgen enable the buzzer generator disable the buzzer generator ' b b#$ 3 8" .b#$ " & ' : ) : $ b 3 HT9580 13 april 28, 2000 preliminary when bz-l and bz-h are all 00h, the tone gen - erator is disabled and bz is high. the value of the frequency divider, ranges from 2 (bz-l=01h, bz-h=00h)~65536 (bz-l=ffh, bz-h=ffh). writing to bz-l only writes the data into a low byte buffer, while writing to bz-h will write the high byte data and the con - tents of the low byte buffer into the pfd coun - ter. when the buzzer generator is disabled by clearing the mgen bit in the configuration register (0000h), the bz pin remains at its last state. if the bz pin is low, the bz transistor in the application circuits is always active. there - fore it is recommended that both bz-l and bz-h be cleared and that the mgen bit in the configuration register (0000h) also be cleared, when it is desired to disable or stop the buzzer. the output of the 16-bit pfd counter is divided by 2 to generate a bz output with or without modulation. for example, if the desired output of bz is 1.6khz with modulation and the fre - quency source is x1-clock (76.8khz), then the value of 16-bit pfd counter is set to bz-l=17h, bz-h=00h and mdut is set high. 7 >= a ; ' b >= a ; (b#$ ? 3 >= a : 03 > ' b & ) &; &; interrupt registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0005h int ctrl 0 0 0 rtcen ormsk rtcmsk tm1imsk tm0imsk 0000 1111 0006h int flag 0 rtc_fg dr_fg bf_fg wdtovfg or_fg tm1ovfg tm0ovfg 0000 0000 there are two interrupts for the HT9580: a non-mask interrupt (nmi) and a generic inter- rupt request (irq). the data ready interrupt and battery fail interrupt share the nmi call lo - cation. which interrupt occurred can be deter - mined by checking bit bf_fg and the data ready interrupt bit dr_fg or spi complete flag spifg (in spi-config register). dr_fg is the data ready interrupt indication bit. when a valid call is detected, data begins to transfer. either one call is terminated or a message buffer is full or one batch is over but the mes - sage is not terminated, the data ready inter - rupt will occur and dr_fg is set high. the dr_fg bit should be cleared low by the c soft - ware after a data ready condition has occurred. a battery fail condition is triggered by a high to low transition on pin baf and will set the bat- tery fail interrupt request flag bf_fg to logic high. for details, refer to the pocsag decoder section. the sources for the irq are timer 0 overflow, timer 1 overflow, out-of-range status changes and rtc time out. the four interrupt sources all could be masked, but the four corre - sponding interrupt flags will still be set when the interrupt conditions are met. all the four flags are readable/writeable. when an inter - rupt condition is met, a flag will be set. if an in - terrupt routine is performed, the software should check which flag is set to high then de - termine what kind of interrupt source occurred. the wdtovfg is the flag for the watchdog HT9580 14 april 28, 2000 preliminary timer overflow and rtc_fg is an indicator for the rtc time out interrupt request flag. the or_fg will be set high when an out-of-range status from low to high or high to low transition occurrs. those flags such as tm0ovfg, tm1ovfg, bf_fg, dr_fg, or_fg and rtc_fg should be cleared by the software af - ter they are activated. 10 rtcen rtc counter is enabled rtc counter is disabled rtcmsk rtc interrupt is masked rtc interrupt is not masked tm0imsk timer 0 overflow interrupt is masked timer0overflow interruptisnot masked tm1imsk timer 1 overflow interrupt is masked timer 1 overflow interrupt is not masked ormsk out-of-range interrupt is masked out-of-range interrupt is not masked 10 tm0ovfg timer 0 overflows no timer 0 overflow tm1ovfg timer 1 overflows no timer 1 overflow wdtovfg watchdog timer has overflown no watchdog timer overflow bf_fg battery fail request no battery fail request dr_fg data ready request no data ready request or_fg out-of-range request no out-of-range request rtc_fg rtc interrupt request no rtc interrupt request 8 9 ?7 =?7 8 a 9=?7 9a a 0 ? $ d block diagram of nmi and irq HT9580 15 april 28, 2000 preliminary a a 9 ?7 9 ?7 $ <6 @ $ <6 @ $ <6 @ $ <6 @ $ <6 @ $ <6 @ $ 0# 9 ?7 0# a 0# 9 ?7 0# 6@ 0# 6@ 0# 6@ 0# 6@ 0# 6@ timer0 and timer1 timing diagram reset conditions the HT9580 will reset the whole chip when the following conditions are met: power on the external reset pin is held low for at least 1 ms the wdt overflows the input is used to reset the c. reset must be held low at least 1 ms after vdd reaches oper- ating voltage from a power down. a positive transition on the chip reset will then cause an initialization sequence to begin. after the sys - tem is operating, a low on this line of at least 1 ms in duration will cause c activity. when a positive edge is detected, there is an initializa- tion sequence lasting 8-clock cycles. then the interrupt mask flag is set, the decimal mode is cleared and the program counter is loaded with the restart vector from locations fffc (low byte) and fffd (high byte). this is the start lo- cation for program control. this input should be high during normal operation. HT9580 16 april 28, 2000 preliminary / 9 4 0f ?$ <$ 3$ @ 0f ?$ <$ 3$ - $/5 / @ / - $/5 <$ 3$ @ , - ???- ??? - ??? - ??? - <$ 3$ - $/5 ???- ????- @ 9 b#$ $44 3 : 9 <6 @ 5$4 7 3 b3 4 9$b93 5$4 )+ power on reset timing :$b93 5$4 " reset active and wdt time-out HT9580 17 april 28, 2000 preliminary timer registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0007h tmrc tmr1mod x tmr1clk tmr0clk tmr1edg tmr0edg tmr1en tmr0en 0u00 0000 0008h tmr1l tm1d7 tm1d6 tm1d5 tm1d4 tm1d3 tm1d2 tm1d1 tm1d0 uuuu uuuu 0009h tmr1h tm1d15 tm1d14 tm1d13 tm1d12 tm1d11 tm1d10 tm1d9 tm1d8 uuuu uuuu 000ah tmr0 tm0d7 tm0d6 tm0d5 tm0d4 tm0d3 tm0d2 tm0d1 tm0d0 uuuu uuuu in addition to the watchdog timer, the HT9580 provides two timers: an 8-bit timer (timer 0) and one 16-bit timer (timer 1). those two timers are controlled and configured by the register tmrc. both timers are programmable up-count coun - ters whose clocks may be derived from the x1-clock (32.768khz, 76.8khz or 153.6khz). to program the timers, tmr0, tmr1l, and tmr1h should be written with a start value. when the timers are enabled, they will count-up from the start value. if the timers overflow, cor - responding interrupts will be generated. when the timers are disabled, the counter contents will not be reset. to reset the counter contents, the software should write the start value again. since timer1 is a 16-bit counter, it is important to note the method of writing data to both tmr1l and tmr1h. writing to tmr1l only writes the data into a low byte buffer, while writ- ing to tmr1h will simultaneously write the high byte data and the contents of the low byte buffer into the timer counter preload register (16-bit). note that the timer counter preload register contents are changed by a tmr1h write operation while writing to tmr1l does not change the contents of the preload register. reading tmr1h will also latch the contents of tmr1l into the byte buffer to avoid false timing problem. reading tmr1l returns the contents of the low byte buffer. in other words, the low byte of the timer counter cannot be read directly. it must first read tmr1h to latch the low byte contents of the timer counter into the buffer. tmrc is the timer counter control register, which defines the timer counter options. the timer1 clock source can be selected from either the internal clock or an external input clock by bit tmr1mod of the tmrc register. the timer0/timer1 can also select its clock source by bits tmr0clk/tmr1clk. tmrc as shown in the table. labels (tmrc0 and tmrc1) bits function tmr0en, tmr1en 0 1 enable/disable timer counting (0=disable; 1=enable) tmr0edg, tmr1edg 2 3 define the tmr0 and tmr1 active edge (0=active on low to high; 1=active on high to low) tmr0clk 4 select tmr0 clock source (0=x1-clock; 1=osc1 input clock/system clock) tmr1clk 5 select tmr1 clock source if internal clock input is selected (0=x1-clock; 1=osc1 input clock/system clock) tmr1mod 7 define the tmr1 operation mode (0=internal clock input; 1=external clock input) HT9580 18 april 28, 2000 preliminary $ 3 0 /$ $ 3 !" b# $% 3 0 9 <6 @ 34 0/ 7 = = ' b a timer 0 block diagram $ 8< 3 0 /$ $ 3 ! (b#$% 3 0 9 <6 @ 3 4 0/ 7 ' b 9 a timer 1 block diagram HT9580 19 april 28, 2000 preliminary the HT9580 has three general purpose i/o ports. the i/o cell structures are configurable. details are shown in the table. port a port a is a general-purpose i/o port. the pac register controls the data directions for port a. when set as input data type, this port has wake-up capability and the input cell struc - tures are schmitt trigger types. while in a halt condition, a falling edge signal on port a can wake-up the c. in addition, the input cell structures can be configured as pull-high or non-pull-high. when set as an output data type, the output structures are cmos outputs. 10 pa the pin output logic high the pin output logic low pac as input pin as output pin pawue the pin has wake-up capability the pin has no wake-up capability paim cmos input structure with pull-high resistor cmos input structure with- out pull-high resistor port b port b is a general-purpose i/o port controlled by the pbc register. the pbim register con - trols the input cell structures: normal cmos inputs or cmos inputs with pull-high resis - tors. 10 pb pin output logic high pin output logic low pbc input pin output pin pbim cmos input structure with pull-high resistor cmos input structure without pull-high resistor port c this is a general-purpose i/o port contolled by the pcc register. the pcim register controls the input cell structures: normal cmos inputs or cmos inputs with pull-high resistors. 10 pc the pin output logic high the pin output logic low pcc as input pin as output pin pcim cmos input structure with pull-high resistor cmos input structure without pull-high resistor i/o port configuration registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 000bh pa data x x pa5 pa4 pa3 pa2 pa1 pa0 uu11 1111 000ch pb data pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 1111 1111 000dh pc data xxxxxxpc1pc0 uuuu uu11 000eh pac x x pac5 pac4 pac3 pac2 pac1 pac0 uu11 1111 000fh pbc pbc7 pbc6 pbc5 pbc4 pbc3 pbc2 pbc1 pbc0 1111 1111 0010h pcc xxxxxx pcc1 pcc0 uuuu uu11 0011h pa wue x x pawue5 pawue4 pawue3 pawue2 pawue1 pawue0 uu00 0000 0012h pa im x x paim5 paim4 paim3 paim2 paim1 paim0 uu11 1111 0013h pb im pbim7 pbim6 pbim5 pbim4 pbim3 pbim2 pbim1 pbim0 1111 1111 0014h pc im xxxxxx pcim1 pcim0 uuuu uu11 HT9580 20 april 28, 2000 preliminary the mask rom bank point register can switch between the internal 2 mbits mask rom or an external up to 2 mbits mask rom space. the se- lection table is based on the following table. the space size of each mask rom bank is 8 kbytes. the bits bp_modm1 and bp_modm0 define whether internal or external mask rom devices are used. (bp_modm1, bp_modm0)=(0, 1), se- lects the internal mask rom device. (bp_modm1, bp_modm0)=(1, 0), selects the external mask rom device. the internal mask rom can switch from bank 0 to bank 31 and the external mask rom can switch from bank 0 to bnak 31 by software programming. in addition, the address range of the internal/external mask romwillallrangefrom1000hto2fffh. the mask rom bank point register selection table is shown in the table. & ' : & 9 5 $ 3$ & 3 b34 $ i/o structure of port a mask rom (character rom) bank point register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0015h mrom-bp bp_modm1 bp_modm0 m_bp5 m_bp4 m_bp3 m_bp2 m_bp1 m_bp0 0000 0000 bp_modm1 bp_modm0 m_bp5 m_bp4 m_bp3 m_bp2 m_bp1 m_bp0 bp value memory area 00xxxxxxx reserved 010000000 internal 2 mbits mask rom (low 8 kbytes) 01 0101111131 internal 2 mbits mask rom (high 8 kbytes) 0110000032 reserved 01 reserved 0111111163 reserved 100000000 external 2 mbits mask rom (low 8 kbytes) 10 1001111131 external 2 mbits mask rom (high 8 kbytes) HT9580 21 april 28, 2000 preliminary if the internal 2 mbits mask rom is placed as shown in the figure and the software program - mer obtains a start address from cns (taiwan) code or a gb (china) code, a0~a17. the follow - ing steps will map from the start address to the bank point register, then the hardware address decode circuit will point to the real 2 mbits space. (if the internal mask rom is selected.) step 1 the formula obtains a0~a18 from the re - ceived gb or cns code. if it is in the lower 2 mbits space, a18=0. otherwise, a18=1 if it is in reserved space. step 2 set (bp_modm1, bp_modm0)=(0, 1) step 3 assign correct m_bp0 ~ m_bp5 as shown: a13 m_bp0 a14 m_bp1 a15 m_bp2 a16 m_bp3 a17 m_bp4 a18 m_bp5 (the bit will be 0 at this condi - tion) step 4 adding $1000 h to a12~a0 to get new hex value $b 3 b 2 b 1 b 0 h. step 5 the following example will load 32 bytes con - tinuous (one chinese word) pattern from the internal mask rom and store them to the start address $c 3 c 2 c 1 c 0 h (if absolute index addressing mode is used). ldx #00h ldy #00h read: lda $b 3 b 2 b 1 b 0 ,x sta $c 3 c 2 c 1 c 0 ,y inx iny cpx #20h bnz read !7 % ! " ; g g% <0 ! " ; g g% - *????- + - ????- ) . " ( , + * ) * ) ." (,+*) * ! h h * h ) % ) ! h h .h "% ! h (h ,h +% ! * h ) h h % HT9580 22 april 28, 2000 preliminary the sram bank point register can switch to ei - ther external 256 kbytes or internal 32 kbytes sram space. the selection table is based on the following table. the space size of each sram bank is 8 kbytes. bits bp_mods1 and bp_mods0 define whether internal or exter - nal sram devices are used. (bp_mods1, bp_mods0)=(0, 1), is for internal sram de - vices. (bp_mods1, bp_mods0)=(1, 0), is for external sram devices. the internal sram would switch from bank 0 to bank 3 and the ex - ternal sram would switch from bank 0 to bank 31 by software programming. in addition, the address range of the internal/external sram will all range from 3000h to 4fffh. sram bank point register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0016h sram-bp bp_mods1 bp_mods0 s_bp5 s_bp4 s_bp3 s_bp2 s_bp1 s_bp0 0000 0000 bp_mods1 bp_mods0 s_bp5 s_bp4 s_bp3 s_bp2 s_bp1 s_bp0 bp value memory area 00xxxxxxx reserved 010000000 internal 32 kbits sram (low 8 kbytes) 01 010000113 internal 32 kbits sram (high 8 kbytes) 010001004 reserved 01 reserved 0111111163 reserved 100000000 external 256 kbits sram (low 8 kbytes) 10 1001111131 external 256 kbits sram (high 8 kbytes) lcd control and data register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0017h lcd_ctrl lcd-chip1 lcd-chip0 lcd-clk clk-mod lcd-cs1 lcd-cs0 lcd-a0 lcd-wrb 0000 1101 0018h lcd_cmd lcd_d7 lcd_d6 lcd_d5 lcd_d4 lcd_d3 lcd_d2 lcd_d1 lcd_d0 uuuu uuuu the lcd control and command registers are used for lcd driver interface. there are three kinds of lcd driver chips available for the HT9580. these lcd drivers are sed15x(ksx) series, motorola lcd driver chip mc141x se - ries and hd66410 respectively according to the following lcd-chip0 and lcd-chip1 bit table settings. the combination of the lcd_cmd and lcd-ctrl registers can con - trol the sed15x(ksx), mc141x series or hd66410 lcd drivers. bits lcd-cs0/1 of the lcd-ctrl register corresponds to the chip se- lect pin of the lcd driver. the bit lcd-cs0 is used to control the master lcd driver chip while lcd-cs1 is for the slave lcd driver chip. both bits are active low. the bit clk_mod is used to enable or disable the pin out of lcd_cl. if the bit is set low, the clock output of pin lcd_cl will be disabled, otherwise the lcd_cl clock will be set accord - ing to the following truth table. HT9580 23 april 28, 2000 preliminary lcd-chip0 and lcd-chip1 truth table lcd-chip0= 0 lcd-chip0= 1 lcd-chip1= 0 sed15x(ksx) series lcd driver is selected mc141x series lcd driver is selected lcd-chip1= 1 hd66410 lcd driver is selected n/a lcd_cl truth table lcd-chip0= 0 lcd-chip0= 1 lcd-chip1= 0 lcd_cl: 2 khz output lcd_cl: if lcd-clk =0, 32 khz output if lcd-clk =1, x1-clock output lcd-chip1= 1 lcd_cl: 10.9khz output n/a the following is a comparison table of the HT9580 pin description between the sed15x (ksx) series and the mc141x series lcd driver. HT9580 (pin) sed15x(ksx) series mc141x series lcd_a0 a0 data/command select input. a0=0: display control data on d0~d7 a0=1: display data on d0~d7 d/c this input pin acknowledges valid data on d0~d7. if high then d0~d7 contains dis - play data, if low d0~d7 con - tains command data. lcd_cs0 cs (master) active low chip select input. (master) ce (master) when high, enables the control pins on the driver. (master) lcd_cs1 cs (slave) active low chip select input. (slave) ce (slave) when high, enables the control pins on the driver. (slave) d0~d7 d0~d7 8-bit, tristate, bidirectional i/o bus. d0~d7 bidirectional bus for data/command transfer. lcd_e e enable clock input cs this pin is normal low clock input. data on d0~d7 is latched at the falling edge of cs. lcd_rw r/w read/write input r/w to read the display data ram or the internal sta - tus, pull this pin high. the pin low indicates a write operation. lcd_cl cl external clock input. (2khz output from HT9580) osc2 oscillator input for external clock is used. (32khz or x1-clock output from HT9580 as determined by the lcd-clk ). HT9580 24 april 28, 2000 preliminary 8: ! <% = ! <% = = =: = = ! % ! % < $< 5 4 4 $ $ $ 3 $@ 5 # $g b - g; 0 g b - g; , * ) ( + , " 8: = ! <% = = =: = = ! % , 8 9) * ) ( + , " < $< 544 $ $ $ 3$@ 5#$g b - g; 0g b - g; ! % ! <% HT9580 25 april 28, 2000 preliminary lcd driver chip selection application note lcd-chip0="0" lcd-chip1="0" sedx(epson) series lcd driver at 68 family mpu appli - cation mode. reset is low active ksx(samsung) series lcd driver at 68 family mpu appli - cation mode. pin options set as 68 family mpu application mode. lcd-chip0="1" lcd-chip1="0" mc14x(motorola) series lcd driver. lcd-chip0="0" lcd-chip1="1" hd66410(hitachi) series lcd driver. sedx(epson) series lcd driver at 80 family mpu application mode. reset is high active ksx(samsung) series lcd driver at 80 family mpu appli- cation. pin options set as 80 family mpu application mode. lcd-chip0="1" lcd-chip1="1" n/a ! <% = ! <% = = =: = = ! % ! % < $< 544 $ $ $ 3$@ 5#$g b - g; 0g b - g; : , * ) ( + , " power down operation halt the halt mode is initiated by setting the con - figuration register bit halt high and results in the following ... the system clock turns off, the low power pager sub-clock, lcd driver, pager decoder and rtc all keep running. the contents of the on-chip ram and of the reg - ister remain unchanged. as the wdt and the wdt prescaler depend on software control, the wdt will continue to count when the halt bit is set high. all the i/o ports remain in their original status. HT9580 26 april 28, 2000 preliminary 8= !8% ( ) ) , ) + ) * ) ) ) ) ) ) =9& 5 6$/3$ 65"b#$ 8 <04 @ 0 @ d/a registers address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 002fh d/a-l da7 da6 da5 da4 da3 da2 da1 da0 0000 0000 0030h d/a-h xxxxx d/a_pd rssi bat uuuu u1uu the system can quit the halt mode by an ex - ternal reset, an interrupt, an external falling edge signal on port a or an rtc time out. the HT9580 has one internal 8-bit d/a con - verter which can measure the battery voltage and the rssi input signal from the if of the rf circuit. the da0~da7 is the digital input of the d/a converter and the analog outputs to the pin named da_out. bit bat of the da-h register (0030h) is the output of the comparator. its in - put at the - terminal is from the d/a output and the + terminal comes from the input pin baf . the bit rssi of da-h register (0030h) is the output of another comparator. its input at - terminal is from the d/a output and ter - minal comes from the input pin rssi. the soft - ware can detect the battery voltage and the rssi signal by writing to the bits da0 ~da7 (002fh) and reading the bits bat, rssi (0030h). bit d/a_pd is used for the d/a power down control. if this bit is logic high, the d/a will be in the power down mode. otherwise, the d/a is in the normal condition. for details see the follow - ing figure. HT9580 27 april 28, 2000 preliminary buffer status register address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 state on por 0031h buffer status msg_end x count_5 count_4 count_3 count_2 count_1 count_0 0uuu uuuu the buffer status register will relay to the c the status of the message buffer when the data ready request interrupt occurred. the msg_end bit will be set high when the data (including address codeword and message code - word) is at the end of this data ready interrupt call. the valid data length of the message buffer is determined by bit count_0 to count_5. if msg_end is low, the data length is more than 46 or data is not at the end, the c should wait for the next data ready interrupt until the bit msg_end is set high. example 1: if the data read from 0031h is 95h when a new data ready interrupt occurred, it means the to - tal data length is 21 including the address code - word in this call and the message is terminated (bit msg_end =1). the figure below illus - trates example 1. / 366 00 0@ 0 / 0@ 0 / 0@ 0) / 0@ 0 . / 0@ 0) 8 + - + - +)- ,*- ,+- ,,- 8 ( - $ $( $, $+ $* $) $ $ * - example 1 HT9580 28 april 28, 2000 preliminary / 366 00 0@ 0 / 0@ 0 / 0@ 0) / 0@ 0++ / 0@ 0+, 8 + - + - +)- ( - ( - ( - $ $( $, $+ $* $) $ $ * - / 366 / 0@ 0+( / 0@ 0+ / 0@ 0+" + - + - +)- / 0@ 0+. +*- / 0@ 0, ++- +,- 8 0 34 $ $( $, $+ $* $) $ $ * - )0 0 34 example 2 example 2: if the data read from 0031h is 2eh when a new data ready interrupt oc - curred, that means the data length of this call is more than 46 and the next data ready interrupt will occur. if the next interrupt occurs and the contents of 0031h is 85h , the result are shown in the following figure. the programmer should note that the information on the mes - sage buffer must be read out before the next continuous codeword arrives. otherwise the data on the message will be overwritten. the data ready interrupt will generate when message is terminated, synchronization code word is received or buffer is full. the following figure will show the typical operation. ? , 9 7 3 3 =?7 / 366 !+(#% ? ( ? ? ? ? ) $0 the timing chart of message buffer spi configure register address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 state on por 0032h spi-config s/m len1 len0 reqst spifg clk_edg spi_en start 0111 1000 HT9580 29 april 28, 2000 preliminary s/m: slave/master mode selection when s/m is "0", HT9580 is in the master mode. otherwise, HT9580 is in the slave mode. 01 s/m master mode (sck is output) slave mode (sck is input) len0, len1: data length the len0 and len1 will determine the data length between exchange. len1 len0 data length (bit) 00 4 01 8 10 16 11 32 reqst: spi request (read only) when flex tm decoder wants to exchange data with HT9580, the reqst will have low pulse. spifg: spi complete flag 0 (clear): data transfer to external device has been completed. 1 (set): no valid completion of data transfer. the bit is cleared by hardware and set by software. clk_edg: data sampling edge the clk_edg will determine the valid miso and mosi sampling edge of sck clock. 01 clk_edg rising edge falling edge spi_en: the spi enable 01 spi_en when the spi cir - cuit is disabled, the pocsag decoder i/o pins will be en - abled the spi cir - cuit and spi i/o pins will be enabled start: the data exchange start or not 01 start no data exchange data exchange start when the bit is set by software, the spi data exchange will start. after the first bit data ex- change is completed, the start bit will clear to low again by hardware. HT9580 30 april 28, 2000 preliminary spi speed register (write only) address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 state on por 0033h spi-speed sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0000 0000 the register will determine the sck clock frequency of spi. when speed register are 00h, the sck clock output is high. the value of the frequency divider, ranging from 1 (speed=01h)~255 (speed=ffh). if speed=00h, the sck output will be disabled. ' b "b#$ 3 a spi output buffer register (write only) address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 state on por 0034h spi-out3 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0035h spi-out2 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0036h spi-out1 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0037h spi-out0 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 the spi-out3~0 are used when transmitting data on the serial bus. only valid data write to the reg - ister spi-out3~0 and "start" initiating will begin the spi data transmission from HT9580 to flex tm decoder. after completion of the 4-byte data transfer, the "spifg" status bit will be set and the internal signal reqst will generate a falling edge signal for nmi. the bit7 of spi-out3 is msb and bit0 of spi-out0 is lsb. ?7 ! % !/$% !/$% /$ - $/5 a 9 !6 - .," % b9 &* b * 9 !6 0 0% ! 0 0% 2 !6 0 0% 4 1 5/$$$0#5- .," ) ) HT9580 31 april 28, 2000 preliminary spi input buffer register (read only) address register name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 state on por 0038h spi-in3 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 0039h spi-in2 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 003ah spi-in1 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 003bh spi-in0 d7 d6 d5 d4 d3 d2 d1 d0 0000 0000 the spi-in3~0 are used when receiving data on the serial bus. when spi transmits only valid data writes to the register spi-out3~0, "start" will initiate the spi data transmission from HT9580 to flex tm decoder. after completion of the 4-byte data transfer, the "spifg" status bit will be set and the internal signal "reqst" will generate a falling edge signal for nmi. the bit7 of spi-in3 is msb and bit0 of spi-in0 is lsb. ?7 ! % !/$% !/$% a 9 !6 - .," % 9 !6 0 0% ! 0 0% 2 !6 0 0% b9 &* b * ) ) 4 1 5/$$$0#5- .," HT9580 32 april 28, 2000 preliminary the pocsag paging code a transmission using the ccir radio paging code no.1 (pocsag code) is generated in ac - cordance with the following rules (see the fol - lowing figure). - -) - iiiiiiiii ? ? ? " 00 $ !! " !!#$ " $3 # ) . ) 8) )) * *) * 0 0 $4 % & " * 5 0 $4 ' ( ) " #$ ) / $ '( ) * * )?3 $ $ #$ * * * * pocsag code structure the transmission is started by sending a pre - amble, consisting of at least 576 continuously alternating bits (10101010...). the preamble is followed by an arbitrary number of batch blocks. only complete batches are transmitted. each batch comprises 17 code-words of 32 bits each. the first code-word is a synchronization code-word with fixed pattern. the sync word is followed by 8 frames (0~7) of 2 code-words each, containing message information. a code-word in a frame can either be an address, message or idle code-word. idle code-words also have fixed patterns and are used to fill empty frames or separate mes- sages. address code-words are identified by an msb of logic 0 and are coded as shown in the pocsag code structure figure. a user address or ric (receiver identity code) consists of 21 bits. only the upper 18 bits are encoded in the ad- dress code-word (bits 2 to 19). the lower 3 bits designate the frame number in which the ad- dress is transmitted. four different call types can be distinguished on each user address. the call type is deter- mined by two functional bits in the address code-word (bits 20 and 21). the pocsag stan- dard recommends the use (in taiwan) of combi- nations of data formats and function bits, as shown in the following table. other combina - tions will be set by spf16~spf19. bit 20 (msb) bit 21 (lsb) call type data format 0 0 numeric 4-bit package 0 1 alert only 1 0 alert only 1 1 alpha-numeric 7-bit package data formats and function bits HT9580 33 april 28, 2000 preliminary alert-only calls consist of a single address code-word. numeric and alphanumeric calls have message code-words following the address. message code-words are identified by an msb of logic 1. the message information is stored in a 20-bit field (bits 2 to 21). the data format is determined by the call type: 4 bits per digit for numeric message and 7 bits per (ascii) charac - ter for alphanumeric messages. each code-word is protected against transmission er - rors by 10 crc check bits (bit 22 to 31) and an even parity bit (bit 32). this permits correction of a maximum of 2 ran - dom errors or up to 4 errors in a burst of 4 bits (a 4-bit burst error) per code-word. error correction item description address code-word two random errors, or 4-bit burst errors (optional) message code-word two random errors, or 4-bit burst errors (optional) error correction in the HT9580, error correction methods have been implemented as shown in the table above. random error correction is the default for both address and message code-word. in an- other method, burst error correction can be switched by spf programming. up to 4 erro- neous bits in a 4-bit burst can be corrected. the error type detected for each code-word is identified in the message data output to the microcontroller, allowing rejection of calls with too many errors. operating states on status standby status the operating state is determined by control address (0019h) bit 0 and monitored by bit 3 of address (0019h). truth table for decoder operating status on input operating status 0 on state 1 standby state on status in the on status, the decoder pulses the re - ceiver, quick charge and pll enable outputs (respectively bs1, bs2 and bs3) according to the code structure and the synchronization algorithm. data received serially at the data input (di) is processed for call receipt. stb status in the stb status the decoder will neither ac - tivate the receiver, quick charge or pll en - able outputs, nor process any data at the data input. the crystal oscillator remains active to permit communication with the microcontrol- ler. battery saving current consumption is reduced by switching the stb internal decoder sections whenever the receiver is not enabled. to further increase battery efficiency, reception and decoding of an address code-word is stopped as soon as the un - corrected address field differs by more than 3-bits from the enabled rics. if the next code-word has to be received again, the receiver is re-enabled, thus observing the programmed establishment times t bs1 ,t bs2 and t bs3 . data reception and buffer reception of a valid paging call is signaled to the microcontroller by means of an interrupt signal. the received address and message code-word can then be read via a 46 bytes message buffer (from 0040h to 006dh) for de- coder data message. if the c did not read the previous message within one code-word time from the message buffer, the message buffer data will be overwritten. bit rates the HT9580 can be configured for data rates of 512, 1200 or 2400 bit/s by spf program - ming. these data rates are derived from 32.768khz, 76.8khz or 153.6khz oscillator frequencies. input data processing the input data is noise filtered by means of a digital filter. data is sampled at 16 times the data rate and averaged by majority decision. HT9580 34 april 28, 2000 preliminary the filtered data is used to synchronize an in - ternal clock generator by monitoring transi - tions. the recovered clock phase can be adjusted in steps of 1/8, 3/32, 1/16, or 1/32 bit period per received bit. all step size are used when bit synchroniza - tion has not been achieved, the smallest when a valid data sequence has been detected. erroneous code-words upon receipt of erroneous uncorrectable code-words, call termination occurs according to the conditions given below: spf08 spf09 description 0x any two consecutive code-words or the code-word directly following the address code-word in error 1 0 any single code-word in error 11 any two consecutive code-words in error message receiving mode the receiving message mode (numeric or al - pha-numeric) depends on bits spf16~spf19. if one of these bits from spf16~spf19 is cleared to low, the decoder will be in numeric package receiving mode. otherwise, the de - coder is in the alphanumeric receiving mode. an example is shown below: function bits message re - ceiving format bit 20 (msb) bit 21 (lsb) spf16=0 00 numeric (4-bit) spf17=0 01 numeric (4-bit) spf18=1 10 alphanumeric (7-bit) spf19=1 11 alphanumeric (7-bit) the decoder data output format is deter - mined by the value spf16~spf19. when it is logic low, the 4-bit (numeric) package will be selected. otherwise, the 7-bit (alphanumeric) package is selected. the following tables illus - trate the above two different conditions. message code-word on the message buffer (numeric receiving mode) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 error flag 0 0 0 d3 d2 d1 d0 message code-word on the message buffer (alphanumeric receiving mode) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 error flag d6 d5 d4 d3 d2 d1 d0 synch word indication the synch word recognized by the HT9580 is the standard pocsag synchronization code-word as shown in the following table. bitno.0123456789101112131415 bit 0111110011010010 bit no. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit 0001010111011000 note: the value of 0019h-bit3 stb is set when decoder enters the standby mode and cleared when de - coder enters the on mode. the value of 0006h-bit4 bf_fg is dependent on the baf pin ststus. the value of 0019h-bit5 or is always changed by an out of range signal. the value of 0019h-bit6 bl is cleared 0" by the decoder battery low signal and set 1" when the c sets this bit high. the value of 0006h-bit5 dr_fg is set 1" by the decoder data-ready interrupt signal and cleared 0 when the c clears dr_fg. HT9580 35 april 28, 2000 preliminary idle word indication the idle word recognized by the HT9580 is a standard pocsag idle code-word as shown in the following table. bitno.0123456789101112131415 bit 0111101010001001 bit no. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 bit 1100000110010111 error indication after error correction, any code-word contain - ing more than 2-bit random errors or 4-bit burst errors (option) in the address or mes - sage code-word may be indicated from the er - ror flag position. decoder and c interface the HT9580 has two c interface available. one is the pager control address (0019h), which controls the operation and configura - tion of the decoder. the other is the pager message bu ffer address (from 0040h to 006dh), which receives the message data of calls in the parallel mode. the data ready (dr_fg) and battery fail (bf_fg) interrupt flags are in the interrupt flag register (0006h). $ $ $) $* $+ $, $( $ 9 9 $ $( $, $+ $* $) $ $ 9 7 0 0 9 343 / 366 !+( % ) * ? ai # 3 $ 3$ ; i. - ; i 0 34 / a ?=?7 ! (- % =?7 ! (- % $+ $, ! % !: 34% .- ? ! ? $ 3 4 % HT9580 36 april 28, 2000 preliminary the decoder control address (0019h) contains a battery low flag (bl ), an out of range flag (or ), decoder standby flag (stb), a decoder software reset (res ), and a decoder on/off control bit (on ). the data ready and battery fail flag are in the interrupt flag register (0006h). it not only records the status information but controls the operation of the decoder. if the flag status of the battery fail (bf_fg) changes from 0 to 1 , the following condi - tions occur. the pager controller generates an interrupt if the value of the data ready interrupt is 0 . the pager controller does not generate any interrupt and no data is transmitted to it if the value of the data ready interrupt is 1 . on the other hand, if the status of the battery fail flag (bf_fg) changes from 1 to 0 , the internal node pa.7 of the pager controller will supply a wake-up function. after the decoder asserts the data ready request, the data ready interrupt is generated and the dr_fg bit (bit 5 of 0006h) is set high; then the data ready in - terrupt subroutine runs to process the call data on the message buffer and resets the dr_fg bit low. the functional bits (on , res ) and indication bits ( stb, or ,bl , bf_fg and dr_fg) are all used to control the status of the decoder which is operated through the pager control address as described in the following table. int flag register (0006h) symbol bit r/w description bf_fg 4 r battery fail indication bit once the decoder detects that the battery fail condition occurred, the bf_fg will go high. dr_fg 5 r/w data ready interrupt indication bit when a valid call is detected, data transfers to the message buffer. the dr_fg bit goes high when the message is terminated within 46 bytes, one batch is at the end during the message receiv- ing or the data buffer is full if the data length is more than 46 bytes. the c software should read the data on the message buffer within one pocsag message codeword (32-bit) time. the c software has to clear the dr_fg bit low. decoder control register (0019h) symbol bit r/w description on 0 r/w on/off control bit this bit selects the on or standby state of the decoder 0: on state 1: standby res if spi circuit is enabled, it would be better if this bit is set high to reduce power consumption. res 1 r/w resets the decoder core output the c has to set the res bit low and then high after the pager controller is turned on. the reset status must be released before writing data to the de - coder configuration ram. HT9580 37 april 28, 2000 preliminary symbol bit r/w description stb 3 r standby indication bit when the value of the on bit is 1, the system goes into the standby state. the standby state allows the c to execute the configuration ram setting. or 5r out-of-range indication bit whenever the decoder detects an out-of-range hold time, that is selected by the configuration registers spf06 and spf07. the out-of-range indication may be tested for an out-of-range condi - tion whenever the interface enable of the decoder is active; other - wise or is normally low. the out-of-range indication is set high by detection of valid data transmission. if the out-of-range indication bit changes the status from high to low or low to high, an interrupt will be generated and the out-of-range hold-off time-out counter starts to count. the bit is not valid when the spi circuit is enabled. bl 6 r/w battery low indication bit the battery low indication is periodically tested for a battery low condition. if the decoder encounters a battery low condition, the battery low indication bit is cleared low. the c can only set the bl bit high. attempting to clear this bit has no effect. the bit is not valid when the spi circuit is enabled. user address format a user address in the pocsag code consists of 21 bits. three of the 21 bits are coded in the frame number and are therefore not explicitly transmitted. in the decoder, the addresses a, b, c, d, e and f can use six different frames respectively. every address has to be explic- itly enabled by resetting the associated en- able bit. example: address decimal value: rica=10535 binary equivalent (14-bit): 10100100100111 binary equivalent (18+3-bit): 000000010100100100111 register allocation a00 a01 a02 a03 a04 a05 a06 0000000 a07 a08 a09 a10 a11 a12 a13 1010010 a14 a15 a16 a17 fa2 fa1 fa0 0100111 HT9580 38 april 28, 2000 preliminary address word format bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sync. state call address dup. call valid address function code note: bit0: bit21 of the address code-word bit1: bit20 of the address code-word bit2: if this bit is 1 , the address word is valid, oterwise the address word is not valid. bit3: 1 for a duplicate code-word bit7: 1 if an address code-word is received in the data fail mode bit6 bit5 bit4 call address 0 0 0 ric a 0 0 1 ric b 0 1 0 ric c 0 1 1 ric d 1 0 0 ric e 1 0 1 ric f 11 0 11 1 interrupt indication the HT9580 provides an internal data ready interrupt and a battery fail interrupt. the in- ternal data ready interrupt and battery fail interrupt share the nmi location. which in- terrupt occurred can be determined by check- ing the battery fail interrupt bit (bf_fg; bit 4 of 0006h) and the data ready interrupt bit (dr_fg; bit 5 of 0006h). both interrupt bits are active high. test mode the test mode of the decoder is selected by set - ting the ts pin low at any time. in the test mode, the rf control outputs bs1 and bs3 are constantly set high, but bs2 is set low. after the ts pin is set high the decoder exits the test mode. message data transfer the decoder outputs a deformatted address word and message words upon receipt of a valid call. the message data to be transferred is or - ganized into 8-bit words and transferred to the message buffer address (0040h to 006dh). the data ready interrupt flag will be set high when the received data (including address code - word and message codeword) length is ter - minated within 46 bytes, one batch is over or if the 46 bytes data buffer is full if data length is more than 46 bytes. if the data in the message buffer is terminated, the msg_end (0031h) bit will set high. the address word indicates call address, func tional bit setting, and decoder flags. the message code-words are received and con - catenated to a valid call address word. the message words are derived from un-cor - rected message code-words. r.f. timing chart HT9580 39 april 28, 2000 preliminary out-of-range indication the out-of-range condition occurs when the time interval defined by spf06, spf07 is un - able to receive sync code words. if sync code words are detected, the timer counter defined by spf06, spf07 will reset. this signal will be seen as a loss of rf signal indication and the power on reset is in an out-of-range condi - tion until the sync code word is detected. duplicate call suppression the HT9580 provides a duplicate call sup - pression with time-out facility, to identify du - plicate call reception. in the display pager mode, duplicate call indication is achieved only via the c interface. a call is assumed to be a duplicate if its latest address and func - tion bit setting is equal to the previous re - ceived call within the time interval defined by spf06, spf07. receiver, quick charge and pll signal control pager receiver, quick charge circuit, and rf pll circuit can be controlled independently via enable outputs bs1, bs2, and bs3 respec - tively. their operating period are optimized according to the synchronization mode of the decoder. each enable signal has its own pro- grammable establishment time. receiver establishment time t bs1 option 512 bps 1200/2400 bps spf00 spf01 7.81ms 53.33ms 0 0 15.63ms 6.67ms 0 1 31.25ms 13.33ms 1 0 62.50ms 26.67ms 1 1 quick charge adjustment time t bs2 option 512 bps 1200/2400 bps spf02 spf03 7.81ms 1.67ms 0 0 15.63ms 6.67ms 0 1 15.63ms 11.67ms 1 0 19.53ms 13.33ms 1 1 pll establishment time t bs3 option 512 bps 1200/2400 bps spf04 spf05 0ms 0ms 0 0 31.25ms 26.67ms 0 1 46.87ms 40.00ms 1 0 62.50ms 53.33ms 1 1 ) * $ ) * HT9580 40 april 28, 2000 preliminary address bit definition bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 001ah ena a00 a01 a02 a03 a04 a05 a06 001bh a07 a08 a09 a10 a11 a12 a13 a14 001ch a15 a16 a17 fa2 fa1 fa0 x x 001dh enb b00 b01 b02 b03 b04 b05 b06 001eh b07 b08 b09 b10 b11 b12 b13 b14 001fh b15 b16 b17 fb2 fb1 fb0 x x 0020h enc c00 c01 c02 c03 c04 c05 c06 0021h c07 c08 c09 c10 c11 c12 c13 c14 0022h c15 c16 c17 fc2 fc1 fc0 x x 0023h end d00 d01 d02 d03 d04 d05 d06 0024h d07 d08 d09 d10 d11 d12 d13 d14 0025h d15 d16 d17 fd2 fd1 fd0 x x 0026h ene e00 e01 e02 e03 e04 e05 e06 0027h e07 e08 e09 e10 e11 e12 e13 e14 0028h e15 e16 e17 fe2 fe1 fe0 x x 0029h enf f00 f01 f02 f03 f04 f05 f06 002ah f07 f08 f09 f10 f11 f12 f13 f14 002bh f15 f16 f17 ff2 ff1 ff0 x x 002ch spf00 spf01 spf02 spf03 spf04 spf05 spf06 spf07 002dh spf08 spf09 spf10 spf11 spf12 spf13 spf14 spf15 002eh spf16 spf17 spf18 spf19 xxxx decoder configuration ram the decoder contains a 21-byte ram to store six user addresses, six frame numbers, and specially programmed function bits (spf00~spf19) for the decoder application configuration. the data memory is mapped to the address 001ah~002eh. the configuration memory mapping table is shown below. HT9580 41 april 28, 2000 preliminary description of the special programmed function bits (spfn) the following features can be selected by appro - priate programming of the specially pro - grammed function bits: spf00~spf01 receiver (bs1) establishment time (for the bs2~bs3 options, refer to spf02~spf05) 00: 7.81ms/512 53.33ms/1200/2400 01: 15.63ms/512 6.67ms/1200/2400 10: 31.25ms/512 13.33ms/1200/2400 11: 62.50ms/512 26.67ms/1200/2400 note: the recommendatory setting is 11. spf02~spf03 rf dc level adjustment (bs2) enable time 00: 7.81ms/512 1.67ms/1200/2400 01: 11.71ms/512 6.67ms/1200/2400 10: 15.63ms/512 11.67ms/1200/2400 11: 19.53ms/512 13.33ms/1200/2400 spf04~spf05 pll (bs3) establishment time 00: 0ms/512 0ms/1200/2400 01: 31.25ms/512 26.67ms/1200/2400 10: 46.87ms/512 40.00ms/1200/2400 11: 62.50ms/512 53.33ms/1200/2400 spf06~spf07 the duplicate call suppress time-out and out-of-range hold-off time-out 00: 30s/512/1200 15s/2400 01: 60s/512/1200 30s/2400 10: 120s/512/1200 60s/2400 11: 240s/512/1200 120s/2400 spf08~spf09 0x: any two consecutive code-words or the code-word directly following the address code-word in error 10: any single code-word in error 11: any two consecutive code-words in error spf10 1: 4-bit burst error correction for address and message code-word 0: 2-bit random error correction for address and message code-word spf11 1: out-of-range hold-off period according to spf06 and spf07 0: out-of-range hold-off period is 0 regardless of spf06 and spf07 baud rate selection bits(spf12,spf13,spf14) spf12 spf13 spf14 connected crystal (hz) baud rate (bps) 0 0 0 32768 512 0 0 1 76.8k 512 0 1 0 76.8k 1200 0 1 1 76.8k 2400 1 0 0 153.6k 512 1 0 1 153.6k 1200 1 1 0 153.6k 2400 note: the (spf12, spf13, spf14) = (0, 1, 0) when power on reset spf15 non-inverting or inverting data input selection 1: inverting input selected for di from rf cir- cuit, referring to di 0: non-inverting input selected for di from rf circuit reserved, should be 0 spf16~spf19 message receiving mode selection depending on the function code (bit20, bit21) 01 spf16 function code (0, 0) is a numeric message function code (0, 0) is an alpha-numeric message spf17 function code (0, 1) is a numeric message function code (0, 1) is an alpha-numeric message spf18 function code (1, 0) is a numeric message function code (1, 0) is an alpha-numeric message spf19 function code (1, 1) is a numeric message function code (1, 1) is analpha-numeric message HT9580 42 april 28, 2000 preliminary cpu core the HT9580 is a high performance pager con - troller specifically designed for use in new gen - eration radio pagers. it is based on the m6502 core. the 6502 microprocessor offers complete hardware and software capability with existing 6500 series of products as well as significant en - hancements. instruction register and decoder instructions fetched from memory are gated onto the internal bus. these instructions are latched into the instruction register then de - coded, along with timing and interrupt signals, to generate control signals for the various regis - ters. timing control unit the timing control unit keeps track of the in - struction cycle being monitored. the unit is set to 0 each time an instruction fetch is executed and is advanced at the beginning of each input clock pulse for as many cycles as required to complete the instruction. each data transfer between registers depends upon decoding the contents of both the instruction register and the timing control unit. there are three major clocks in the c as follows: phase 2 in (phi2 (in)) this signal is from the osc1 input pin of HT9580. the phi1 (out) and phi2 (out) are derived from this signal. phase 2 out (phi2 (out)) this signal is generated from phi2 (in). phi2 (in) provides the system timing. there is a slight delay from phi2 (in). phase 1 out (phi1 (out)) inverted phi2 (out) signal. there is a slight delay from phin2 (in). read/write this signal is normally in a high state indicat - ing that the c is reading data from the data bus memory. in the low state the data bus has valid data from the c to be stored at the ad - dressed memory location. parameter description t cyc clock cycle time (min) t ad address delay time t ah address hold time t dis read data in setup time t dih read data in hold time t dod write data out delay time t doh write data out hold time t denbd dataen delay time t wed we_n delay time t syd sync delay time t syh sync hold time t vd vpb delay time t vh vpb hold time t sos sob_n setup time t soh sob_n hold time t rds rdy setup time t rdh rdy hold time t ress res_n setup time t resh res_n hold time timing parameter annotations arithmetic and logic unit all arithmetic and logic operations take place within the alu including incrementing and decrementing internal registers (except for the program counter). the alu has no internal memory and is used only to perform logical and transient numerical operations. HT9580 43 april 28, 2000 preliminary a 9 := 2h 2h = 9 = 0 5 00 : 00 0$ : 0$5 0 0 0 5 0#0 @0 0 h <0 5 h <5 0 5 h 5 h 5 0 h h m6502 read and write cycle accumulator the accumulator is a general purpose 8-bit reg- ister which stores the results of most arithme- tic and logic operations. in addition, the accumulator usually contains one of the two data words used in these operations. index register there are two 8-bit index register (x and y) which may be used to count program steps or to provide an index value to be used in generating an effective address. when executing an in - struction which specifies indexed addressing, the c fetches the opcode and the base address, and modifies the address by adding the index register to it prior to performing the desired op - eration. pre- or post-indexing of indirect ad - dresses is possible. processor status register the 8-bit processor status register contains seven status flags. some of the flags are con- trolled by the program, others may be con- trolled both by the program and the c. the HT9580 instruction set contains a number of conditional branch instructions which are de - signed to allow testing of these flags. program counter the 16-bit program counter register provides the addresses which step the c through se - quential program instructions. each time the HT9580 fetches an instruction from the pro - gram memory, the lower byte of the program counter (pcl) is placed on the low-order bits of the address bus and the higher byte of the pro - gram counter (pch) is placed on the high-order HT9580 44 april 28, 2000 preliminary 8 bits. the counter is incremented each time an instruction or data is fetched from the program memory. stack pointer the stack pointer is an 8-bit register which is used to control the addressing of the vari - able-length stack. the stack pointer is auto - matically incremented and decremented under control of the microprocessor to perform stack manipulations under direction of either the program or interrupt (nmi and irq). the stack allows simple implementation of nested sub - routines and multiple level interrupts. the stack pointer is initialized by the user s soft - ware. status register nvebd i zc note: c: carry 1=true z: zero 1=true i: irq 1=disable d: decimal mode 1=true b: brk command 1=brk, 0=irq e: expansion bit (reserved) v: overflow 1=true n: negative 1=negative 3 3 2 01 /$2 ' 01 /$' / 3 $ ," - 5@ $05 65 4 0$//$ , HT9580 45 april 28, 2000 preliminary interrupt system the HT9580 is capable of directly addressing 64 kbytes of memory. the address space has special significance within certain addressing modes, as follows: reset and interrupt vectors the reset and interrupt vectors use the major - ity of the fixed addresses between fffa and ffff. stack the stack may use memory from 01d0 to 01ff. the effective address of stack and stack relative addressing modes will always be within this range. interrupt request irq this cmos compatible signal requests that an interrupt sequence begin within the c. the irq is sampled during phi2 operation; if the interrupt flag in the processor status register is 0, the current instruction is completed and the interrupt sequence begins during phi1. the program counter and processor status register are stored in the stack. the c will then set the interrupt mask flag high so that no further in- terrupts may occur. at the end of this cycle, the pcl will be loaded from address fffe, and pch from location ffff, transferring program control to the memory vector located at these addresses. the irq signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt handler. the first byte is the high byte in the program coun - ter. the second byte is the program counter low byte. the third byte is the status register value. these values are used to return the processor to its original state prior to the irq interrupt. non-maskable interrupt nmi a negative-going edge on this input requests that a non-maskable interrupt sequence be generated within the c. the nmi is sampled during phi2; the current instruction is com - pleted and the interrupt sequence begins dur - ing phi1. the program counter is loaded with the interrupt vector from locations fffa (low byte) and fffb (high byte), thereby transfer - ring program control to the non-maskable in - terrupt routine. the nmi is generated from data ready interrupt or battery fail interrupt flag (0006h). however, it should be noted that this is an edge-sensitive input. as a result, an - other interrupt will occur if there is another negative-going transition and the program has not returned. also, no interrupt will occur if nmi is low and a negative-going edge has not occurred since the last non-maskable interrupt. the nmi signal going low causes 3 bytes of in - formation to be pushed onto the stack before jumping to the interrupt handler. the first byte is the high byte in the program counter. the second byte is the program counter low byte. the third byte is the status register value. these values are used to return to its original state prior to nmi interrupt. data address space the c internal address bus consists of a0~a15 forming a 16-bit address bus for memory and i/o exchanges on the data bus. the output of each address line is cmos compatible. the ad- dress output pins of HT9580 (a0~a15) derive from c internal address pins a0~a15. the ex- tended address pins (ra14~ra18) are the com- bination of bank point registers (0015h, 0016h) and internal address. the extended ad- dress pins are used to access internal/external sram or mask rom (character rom). the data lines constitute 8-bit bidirectional data bus for use during exchanges between the c and peripherals. the outputs are three-state buffers capable of driving cmos load. the program address and data address space is continuous throughout the 64 kbyte address space. words, arrays, records, or any data structures may span the 64 kbytes ad - dress space. the following addressing mode de - scriptions provide additional detail as to how effective addresses are calculated. fifteen ad - dressing modes are available for the HT9580 as illustrated on the next page. HT9580 46 april 28, 2000 preliminary addressing modes the m6502 supports fifteen (15) addressing modes, shown in table below. in interpreting this table you should note that: the byte following a 2 byte opcode = ial (typ.) the 2 bytes following a 3 byte opcode = bal and bah (typ.) standard assembly notation is used a number in parenthesis indicates that the contents of the location pointed to by the number are to be used. for example (12h) in - dicates the contents of address 12h. a comma in the address is used to indicate the high and low byte of an address. for example (01h, aah) indicates the contents of address 01aah. mode description imp implied: the data is implied in the opcode (example: clc) acc accumulator: the accumulator is used as the source data. (data=areg) imm immediate: the byte following the opcode is the data. (data=ial) zpg zero page: the first 256 ram locations (0000h~00ffh) are used for fast access and small code size. the upper 8-bit of the address are always zero. [data=(00, ial)] zpx zero page indirect x: the x register is added to the byte following the opcode to give a new zero page address. note that the upper 8-bit of the address are always zero. [data=(00, ial+x)] zpy zero page indirect y: the y register is added to the byte following the opcode to give a new zero page address. note that the upper 8-bit of the address are always zero. only the ldx and the stx opcodes use this mode. [data=(00, ial+y)] abs absolute: the two bytes following the opcode give the absolute address of the data. [data=(bah, bal)] abx absolute x: the x register is added to the two bytes following the opcode to produce a new 16-bit address. {data=[(bah, bal)]+x} aby absolute y: the y register is added to the two bytes following the opcode to produce a new 16-bit address. {data=[(bah, bal)]+y} abi absolute indirect: the two bytes following the opcode are used as a pointer to memory. only the jmp opcode uses this mode. [data=(bah, bal)] aix indexed absolute indirect x: the two bytes following the opcode are added to the x register to yield a new 16-bit address. the contents of this address and the fol - lowing one are used as an indirect address. only the jmp opcode uses this mode. {data=[(bah, bal+x+1), (bah, bal+x)]} ind indirect: the byte following the opcode is used as a pointer to the zero page. the contents of this address and the following one are used as the address to finally access the data. {data=[(ial+1), (ial)]} HT9580 47 april 28, 2000 preliminary mode description inx indirect x: the byte following the opcode is added to the x register to produce a new zero page address. the contents of this address and the following one are used as the address to finally access the data. note that when the x register is added to the byte following the opcode, the upper byte of the address is always zero. {data=[(00, ial+x+1), (00, ial+x)]} iny indirect y: the byte following the opcode is a zero page address. the contents of this location and the next one produce a 16-bit address which is then added to the y register to finally obtain the data. {data=<[(00, ial+1), (00, ial)]+y>} rel relative: the byte following the opcode is added in 2's complement fashion to the pc. the byte is sign extended. used by branching instructions. application circuits osc1, osc2 require an external resistor HT9580 48 april 28, 2000 preliminary ? > * ) * * ) i, ) + a 9 + j b i, * , , : * : ) : i, 3ee ' , 9& j )) ? + - 5 $ 0 - , * ) )) ? j -. < $4 ! i, % - .* +( - / i ? i, 4 (" + + -. , i ? i ? , 9 * + , 9 ' ') =9& 9 9) (i" - e / 0 1) 20 (#&3 3 '-! 40- (#& a= : 9 8: = = : = ! % = ! <% = = h),h,( (, (+ (* () ," ( ,. ,, ( . " ( ) " . ( ) h, h " +. +( + +" ++ (( ) * ,* ,+ = 9 )( 4 = 9 - ) , ) / 9 osc1, osc2 do not require a resistor. the osc1 clock comes from an internal pad df only HT9580 49 april 28, 2000 preliminary ? > * ) * * ) i, ) + a 9 + j b i, * , , : * : ) : i, 3ee ' , 9& j )) ? + - 5 $ 0 - , * ) )) ? j -. < $4 ! i, % - .* +( - / i ? i, 4 (" + + -. , i ? i ? , , 9 ' ') =9& 9 9) (i" - e ? ,*i( - e / 0 1 ) 2 0 ( # &3 3 ' -! 4 0- ( # & = = : = ! % = ! <% = = h),h,( (, (+ (* () ," ( ,. ,, ( . " ) ) h, h " +. +( + +" ++ (( ) * ,* ,+ = 9 )( 4 - ) , ) / 9 9 * + a= : 9 8: " . ( = 9 the spi application circuits HT9580 50 april 28, 2000 preliminary ? > * ) * a 9 i, ) + 9 a 9 + j b * , , : * : ) : i, 3ee ' , 9& j )) ? + - 5 $ 0 - , * ) )) ? j -. < $4 ! i, % - .* +( - / i ? i, 4 (" & 2 2 , i ? i ? , , 9 ' ') =9& 9 9) (i" - e / 0 1) 20 (#&3 3 '-! 40- (#& = = : = ! % = ! <% = = h) , h, ( (, (+ (* () ," ( ,. ,, ( . " ( ) ) h, h " +. +( + +" ++ (( ) * ,* ,+ i, + + -. = 9 )( 4 - ) , ) / 9 9 * + a= : 9 8: " . ( = 9 detailed instruction operation the table below provides a brief description of each opcode. the first column lists the name or the assembler mnemonic for the instruction. the second column lists the opcode in hexadecimal. the third column lists the address mode for the instruction. the flags column indicates which of the 8-bit of flags are updated by the instruction. legend: no change + updated 6 from memory bit 6 7 from memory bit 7 the number of bytes column gives the number of bytes for the opcode. the number of cycles column gives the number of clock cycles for the opcode. (a+b indicates one addi - tional cycle when a branch is taken within the same page, or 2 cycles if the branch is to a different page.) the last column are the description or brief descriptions of the opcode. the operator notation is as follows: => assignment + 2 s complement add 2 s complement subtract | bitwise or & bitwise and ^ bitwise exclusive or ! bitwise invert (one s complement) << left rotate >> right rotate < left shift > right shift a accumulator c carry flag x x index register y y index register s stack pointer m memory HT9580 51 april 28, 2000 preliminary name opcode addr mode flags no. bytes no. cyc. description nvebd i zc adc 69 imm ++----++ 2 2 a+m+c=>a, c add with carry adc 65 zpg ++----++ 2 3 a+m+c=>a, c add with carry adc 75 zpx ++----++ 2 4 a+m+c=>a, c add with carry adc 6d abs ++----++ 3 4 a+m+c=>a, c add with carry adc 7d abx ++----++ 3 4 a+m+c=>a, c add with carry adc 79 aby ++----++ 3 4 a+m+c=>a, c add with carry adc 72 ind ++----++ 2 5 a+m+c=>a, c add with carry adc 61 idx ++----++ 2 6 a+m+c=>a, c add with carry adc 71 idy ++----++ 2 5 a+m+c=>a, c add with carry and 29 imm +-----+- 2 2 a&m=>a and a with m and 25 zpg +-----+- 2 3 a&m=>a and a with m and 35 zpx +-----+- 2 4 a&m=>a and a with m and 2d abs +-----+- 3 4 a&m=>a and a with m and 3d abx +-----+- 3 4 a&m=>a and a with m and 39 aby +-----+- 3 4 a&m=>a and a with m and 32 ind +-----+- 2 5 a&m=>a and a with m and 21 idx +-----+- 2 6 a&m=>a and a with m and 31 idy +-----+- 2 5 a&m=>a and a with m asl 0a acc +-----++ 1 2 a<1=>a shift left 1, c<-7, 0<-zero asl 06 zpg +-----++ 2 5 m<1=>m shift left 1, c<-7, 0<-zero asl 16 zpx +-----++ 2 6 m<1=>m shift left 1, c<-7, 0<-zero asl 0e abs +-----++ 3 6 m<1=>m shift left 1, c<-7, 0<-zero asl 1e abx +-----++ 3 7 m<1=>m shift left 1, c<-7, 0<-zero bbr0 0f rel -------- 3 5+b ifm (0)=0, pc<=pc+off (off sign ext) bbr1 1f rel -------- 3 5+b ifm (1)=0, pc<=pc+off (off sign ext) bbr2 2f rel -------- 3 5+b ifm (2)=0, pc<=pc+off (off sign ext) bbr3 3f rel -------- 3 5+b ifm (3)=0, pc<=pc+off (off sign ext) bbr4 4f rel -------- 3 5+b ifm (4)=0, pc<=pc+off (off sign ext) bbr5 5f rel -------- 3 5+b ifm (5)=0, pc<=pc+off (off sign ext) bbr6 6f rel -------- 3 5+b ifm (6)=0, pc<=pc+off (off sign ext) bbr7 7f rel -------- 3 5+b ifm (7)=0, pc<=pc+off (off sign ext) bbs0 8f rel -------- 3 5+b ifm (0)=1, pc<=pc+off (off sign ext) bbs1 9f rel -------- 3 5+b ifm (1)=1, pc<=pc+off (off sign ext) bbs2 af rel -------- 3 5+b ifm (2)=1, pc<=pc+off (off sign ext) bbs3 bf rel -------- 3 5+b ifm (3)=1, pc<=pc+off (off sign ext) bbs4 cf rel -------- 3 5+b ifm (4)=1, pc<=pc+off (off sign ext) HT9580 52 april 28, 2000 preliminary name opcode addr mode flags no. bytes no. cyc. description nvebd i zc bbs5 df rel -------- 3 5+b ifm (5)=1, pc<=pc+off (off sign ext) bbs6 ef rel -------- 3 5+b ifm (6)=1, pc<=pc+off (off sign ext) bbs7 ff rel -------- 3 5+b ifm (7)=1, pc<=pc+off (off sign ext) bcc 90 rel -------- 2 2+b if c=0, pc<=pc+m (msign extended) bcs b0 rel -------- 2 2+b if c=1, pc<=pc+m (msign extended) beq f0 rel -------- 2 2+b if z=1, pc<=pc+m (msign extended) bit 89 imm 7 6 - - - - + - 2 2 a&m=>z, m7=>n, m6=>v bit 24 zpg 7 6 - - - - + - 2 3 a&m=>z, m7=>n, m6=>v bit 34 zpx 7 6 - - - - + - 2 4 a&m=>z, m7=>n, m6=>v bit 2c abs 7 6 - - - - + - 3 4 a&m=>z, m7=>n, m6=>v bit 3c abx 7 6 - - - - + - 3 4 a&m=>z, m7=>n, m6=>v bmi 30 rel -------- 2 2+b if n=1, pc<=pc+m (msign extended) bne d0 rel -------- 2 2+b if z=0, pc<=pc+m (msign extended) bpl 10 rel -------- 2 2+b if n=0, pc<=pc+m (msign extended) bra 80 rel -------- 2 2+b pc<=pc+m (msign extended) brk 00 imp -----1-- 1 7 setb, push pc & psr, pc<=(fffe), set 1 bvc 50 rel -------- 2 2+b if v=0, pc<=pc+m (msign extended) bvs 70 rel -------- 2 2+b if v=1, pc<=pc+m (msign extended) clc 18 imp -------0 1 2 c<=0 cld d8 imp - - - - 0 - - - 1 2 d<=0 cli 58 imp -----0-- 1 2 i<=0 clv b8 imp -0------ 1 2 v<=0 cmp c9 imm +-----++ 2 2 a-m=>n, z, c cmp c5 zpg +-----++ 2 3 a-m=>n, z, c cmp d5 zpx +-----++ 2 4 a-m=>n, z, c cmp cd abs +-----++ 3 4 a-m=>n, z, c cmp dd abx +-----++ 3 4 a-m=>n, z, c cmp d9 aby +-----++ 3 4 a-m=>n, z, c cmp d2 ind +-----++ 2 5 a-m=>n, z, c cmp c1 inx +-----++ 2 6 a-m=>n, z, c cmp d1 iny +-----++ 2 5 a-m=>n, z, c cpx e0 imm +-----++ 2 2 x-m=>n, z, c cpx e4 zpg +-----++ 2 3 x-m=>n, z, c cpx ec abs +-----++ 3 4 x-m=>n, z, c cpy c0 imm +-----++ 2 2 y -m=>n, z, c cpy c4 zpg +-----++ 2 3 y -m=>n, z, c HT9580 53 april 28, 2000 preliminary name opcode addr mode flags no. bytes no. cyc. description nvebd i zc cpy cc abs +-----++ 3 4 y -m=>n, z, c dec c6 zpg +-----+- 2 5 m<=m -1 dec d6 zpx +-----+- 2 6 m<=m -1 dec ce abs +-----+- 3 6 m<=m -1 dec de abx +-----+- 3 7 m<=m -1 dec 3a acc +-----+- 1 2 a<=a -1 dex ca imp +-----+- 1 2 x<=x -1 dey 88 imp +-----+- 1 2 y<=y -1 eor 49 imm +-----+- 2 2 a<=a^m eor 45 zpg +-----+- 2 3 a<=a^m eor 55 zpx +-----+- 2 4 a<=a^m eor 4d abs +-----+- 3 4 a<=a^m eor 5d abx +-----+- 3 4 a<=a^m eor 59 aby +-----+- 3 4 a<=a^m eor 52 ind +-----+- 2 5 a<=a^m eor 41 inx +-----+- 2 6 a<=a^m eor 51 iny +-----+- 2 5 a<=a^m inc e6 zpg +-----+- 2 5 m<=m+1 inc f6 zpx +-----+- 2 6 m<=m+1 inc ee abs +-----+- 3 6 m<=m+1 inc fe abx +-----+- 3 7 m<=m+1 inc 1a acc +-----+- 1 2 a<=a+1 inx e8 imp +-----+- 1 2 x<=x+1 iny c8 imp +-----+- 1 2 y<=y+1 jmp 4c abs -------- 3 3 pc name opcode addr mode flags no. bytes no. cyc. description nvebd i zc lda b1 iny +-----+- 2 5 a<=m ldx a2 imm +-----+- 2 2 x<=m ldx a6 zpg +-----+- 2 3 x<=m ldx b6 zpy +-----+- 2 4 x<=m ldx ae abs +-----+- 3 4 x<=m ldx be aby +-----+- 3 4 x<=m ldy a0 imm +-----+- 2 2 y<=m ldy a4 zpg +-----+- 2 3 y<=m ldy b4 zpx +-----+- 2 4 y<=m ldy ac abs +-----+- 3 4 y<=m ldy bc abx +-----+- 3 4 y<=m lsr 4a acc 0-----++ 1 2 m<=m>1 shift right 1, zero ->7, 0->c lsr 46 zpg 0-----++ 2 5 m<=m>1 shift right 1, zero ->7, 0->c lsr 56 zpx 0-----++ 2 6 m<=m>1 shift right 1, zero ->7, 0->c lsr 4e abs 0-----++ 3 6 m<=m>1 shift right 1, zero ->7, 0->c lsr 5e abx 0-----++ 3 7 m<=m>1 shift right 1, zero ->7, 0->c nop ea imp -------- 1 2 no operation ora 09 imm +-----+- 2 2 a<=a|m ora 05 zpg +-----+- 2 3 a<=a|m ora 15 zpx +-----+- 2 4 a<=a|m ora 0d abs +-----+- 3 4 a<=a|m ora 1d abx +-----+- 3 4 a<=a|m ora 19 aby +-----+- 3 4 a<=a|m ora 12 ind +-----+- 2 5 a<=a|m ora 01 inx +-----+- 2 6 a<=a|m ora 11 iny +-----+- 2 5 a<=a|m pha 48 imp -------- 1 3 push a on stack php 08 imp -------- 1 3 push status on stack phx da imp -------- 1 3 push x on stack phy 5a imp -------- 1 3 push y on stack pla 68 imp +-----+- 1 3 pull a from stack plp 28 imp from stack 1 3 pull status from stack plx fa imp +-----+- 1 3 pull x from stack ply 7a imp +-----+- 1 3 pull y from stack rmb0 07 zpg -------- 2 4 m(0) <=0 (rmw) rmb1 17 zpg -------- 2 4 m(1) <=0 (rmw) HT9580 55 april 28, 2000 preliminary name opcode addr mode flags no. bytes no. cyc. description nvebd i zc rmb2 27 zpg -------- 2 4 m(2) <=0 (rmw) rmb3 37 zpg -------- 2 4 m(3) <=0 (rmw) rmb4 47 zpg -------- 2 4 m(4) <=0 (rmw) rmb5 57 zpg -------- 2 4 m(5) <=0 (rmw) rmb6 67 zpg -------- 2 4 m(6) <=0 (rmw) rmb7 77 zpg -------- 2 4 m(7) <=0 (rmw) rol 2a acc +-----++ 1 2 m<=m<<1, rotate left 1, c<-7, 0<-c rol 26 zpg +-----++ 2 5 m<=m<<1, rotate left 1, c<-7, 0<-c rol 36 zpx +-----++ 2 6 m<=m<<1, rotate left 1, c<-7, 0<-c rol 2e abs +-----++ 3 6 m<=m<<1, rotate left 1, c<-7, 0<-c rol 3e abx +-----++ 3 7 m<=m<<1, rotate left 1, c<-7, 0<-c ror 6a acc +-----++ 1 2 m<=m<<1, rotate right 1, c<-7, 0<-c ror 66 zpg +-----++ 2 5 m<=m<<1, rotate right 1, c<-7, 0<-c ror 76 zpx +-----++ 2 6 m<=m<<1, rotate right 1, c<-7, 0<-c ror 6e abs +-----++ 3 6 m<=m<<1, rotate right 1, c<-7, 0<-c ror 7e abx +-----++ 3 7 m<=m<<1, rotate right 1, c<-7, 0<-c rti 40 imp from stack 1 5 pc<=from stack, b=0 rts 60 imp -------- 1 5 pc<=from stack sbc e9 imm ++----++ 2 2 a<=a-m-c (c is a borrow) sbc e5 zpg ++----++ 2 3 a<=a-m-c (c is a borrow) sbc f5 zpx ++----++ 2 4 a<=a-m-c (c is a borrow) sbc ed abs ++----++ 3 4 a<=a-m-c (c is a borrow) sbc fd abx ++----++ 3 4 a<=a-m-c (c is a borrow) sbc f9 aby ++----++ 3 4 a<=a-m-c (c is a borrow) sbc f2 ind ++----++ 3 5 a<=a-m-c (c is a borrow) sbc e1 inx ++----++ 3 6 a<=a-m-c (c is a borrow) sbc f1 iny ++----++ 3 5 a<=a-m-c (c is a borrow) sec 38 imp -------1 1 2 c<=1 sed f8 imp - - - - 1 - - - 1 2 d<=1 sei 78 imp -----1-- 1 2 i<=1 smb0 87 zpg -------- 2 4 m(0) <=1 (rmw) smb1 97 zpg -------- 2 4 m(1) <=1 (rmw) smb2 a7 zpg -------- 2 4 m(2) <=1 (rmw) smb3 b7 zpg -------- 2 4 m(3) <=1 (rmw) smb4 c7 zpg -------- 2 4 m(4) <=1 (rmw) smb5 d7 zpg -------- 2 4 m(5) <=1 (rmw) HT9580 56 april 28, 2000 preliminary name opcode addr mode flags no. bytes no. cyc. description nvebd i zc smb6 e7 zpg -------- 2 4 m(6) <=1 (rmw) smb7 f7 zpg -------- 2 4 m(7) <=1 (rmw) sta 85 zpg -------- 2 3 m<=a sta 95 zpx -------- 2 4 m<=a sta 8d abs -------- 3 4 m<=a sta 9d abx -------- 3 4 m<=a sta 99 aby -------- 3 4 m<=a sta 81 inx -------- 2 6 m<=a sta 91 iny -------- 2 5 m<=a stx 86 zpg -------- 2 3 m<=x stx 96 zpy -------- 2 4 m<=x stx 8e abs -------- 3 4 m<=x sty 84 zpg -------- 2 3 m<=y sty 94 zpx -------- 2 4 m<=y sty 8c abs -------- 3 4 m<=y stz 64 zpg -------- 2 3 m<=0 stz 74 zpx -------- 2 4 m<=0 stz 9c abs -------- 3 4 m<=0 stz 9e abx -------- 3 5 m<=0 tax aa imp +-----+- 1 2 x<=a tay a8 imp +-----+- 1 2 y<=a trb 14 zpg ------+- 2 5 m<=!a&m, z=a&m trb 1c abs ------+- 3 6 m<=!a&m, z=a&m tsb 04 zpg ------+- 2 6 m<=a|m, z=a&m tsb 0c abs ------+- 3 7 m<=a|m, z=a&m tsx ba imp +-----+- 1 2 x<=s txa 8a imp +-----+- 1 2 a<=x txs 9a imp -------- 1 2 s<=x tya 98 imp +-----+- 1 2 a<=y HT9580 57 april 28, 2000 preliminary opcode matrix the table below shows the matrix of m6502 opcodes: lsb msb 0123456789abcdef 0 brk imp ora inx tsb zpg ora zpg asl zpg rb0 zpg php imp ora imm asl acc tsb abs ora abs asl abs br0 zpg 1 bpl rel ora iny ora ind trb zpg ora zpx asl zpx rb1 zpg clc imp ora aby inc acc trb abs ora abx asl abx br1 zpg 2 jsr abs and inx bit zpg and zpg rol zpg rb2 zpg plp imp and imm rol acc bit abs and abs rol abs br2 zpg 3 bmi rel and iny and ind bit zpx and zpx rol zpx rb3 zpg sec imp and aby dec acc bit abx and abx rol abx br3 zpg 4 rti imp eor inx eor zpg lsr zpg rb4 zpg pha imp eor imm lsr acc jmp abs eor abs lsr abs br4 zpg 5 bvc rel eor iny eor ind eor zpx lsr zpx rb5 zpg cli imp eor aby phy imp eor abx lsr abx br5 zpg 6 rts imp adc inx stz zpg adc zpg ror zpg rb6 zpg pla imp adc imm ror acc jmp abi adc abs ror abs br6 zpg 7 bvs rel adc iny adc ind stz zpx adc zpx ror zpx rb7 zpg sei imp adc aby ply imp jmp aix adc abx ror abx br7 zpg 8 bra rel sta inx sty zpg sta zpg stx zpg sb0 zpg dey imp bit imm txa imp sty abs sta abs stx abs bs0 zpg 9 bcc rel sta iny sta ind sty zpx sta zpx stx zpy sb1 zpg tya imp sta aby txs imp stz abs sta abx stz abx bs1 zpg a ldy imm lda inx ldx imm ldy zpg lda zpg ldx zpg sb2 zpg tay imp lda imm tax imp ldy abs lda abs ldx abs bs2 zpg b bcs rel lda iny lda ind ldy zpx lda zpx ldx zpy sb3 zpg clv imp lda aby tsx imp ldy abx lda abx ldx aby bs3 zpg c cpy imm cmp inx cpy zpg cmp zpg dec zpg sb4 zpg iny imp cmp imm dex imp cpy abs cmp abs dec abs bs4 zpg d bne rel cmp iny cmp ind cmp zpx dec zpx sb5 zpg cld imp cmp aby phx imp cmp abx dec abx bs5 zpg e cpx imm sbc inx cpx zpg sbc zpg inc zpg sb6 zpg inx imp sbc imm nop imp cpx abs sbc abs inc abs bs6 zpg f beq rel sbc iny sbc ind sbc zpx inc zpx sb7 zpg sed imp sbc aby plx imp sbc abx inc abx bs7 zpg HT9580 58 april 28, 2000 preliminary application note the lcd_ctrl and lcd_cmd registers are used to control the lcd drivers. the following exam - ple shows how to initiate the mc141803 lcd driver. the following bit settings are used for the lcd_ctrl register. ; ************ ; * lcd control * ; ************ chip1 set 7 ; select hd66410 series lcd driver 1:hd; chip0 don t care chip0 set 6 ; select sed15x (ksx)/mc141x series lcd driver 0:sed, 1:mc clk set 5 ; lcd clock output selection ; just for mc141x series cmod set 4 ; enable/disable lcd_cl cs1 set 3 ; control master lcd driver chip select cs0 set 2 ; control slave lcd driver chip select a0 set 1 ; data/command select 1:display data on d0~d7 ;data/command select 0:display control data on d0~d7 rw set 0 ; lcd read/write input 0:write 1:read lcdct equ 17h ; lcd control register lcdcm equ 18h ; lcd command register the following three macros define three different modes including lcd command write , lcd data write and lcd data read modes. ; *************************** ; lcdm command mode ; lcd_a0=0 command mode ; lcd_wrb=0 write mode ; command store to acc ; *************************** lcd_c macro rmb a0, lcdct rmb rw, lcdct sta lcdcm smb rw, lcdct endm HT9580 59 april 28, 2000 preliminary ; *************************** ; lcdm write mode ; lcd_a0=1 data mode ; lcd_wrb=0 write mode ; data store to acc ; *************************** lcd_w macro smb a0, lcdct rmb rw, lcdct sta lcdcm rmb a0, lcdct smb rw, lcdct endm ; *************************** ; lcdm read mode ; lcd_a0=1 data mode : lcd_wrb=1 read mode ; data store to acc ; *************************** lcd_r macro smb a0, lcdct smb rw, lcdct lda lcdcm rmb a0, lcdct endm HT9580 60 april 28, 2000 preliminary the following subroutine will initiate the mc141803 lcd driver. ; *************************** ; * initial lcdm * ; *************************** ini_lcdm: lda #01011001b ; mc141x series lcd driver sta lcdct ; enable lcd_cl, lcd_cl=32khz ; lcd_cs0 (master) enable lda #76h ; normal operation lcd_c lda #7bh ; set external clock lcd_c ; feed clock in osc2 from lcd_cl lda #7fh ; set oscillator enable lcd_c lda #2bh ; set dc/dc converter on lcd_c lda #2dh ; set internal regulator on lcd_c lda #31h ; set internal contrast control on lcd_c lda #2fh ; set internal voltage divider on lcd_c lda #33h ; set 50khz to get frame frequency lcd_c lda #29h ; set display on lcd_c lda #36h ; master clear gddram lcd_c lda #0h ; dummy write data lcd_w lda #04h ; change to page 5 if want to clear icon line lcd_c lda #37h ; master clear icons lcd_c lda #0h ; dummy write data lcd_w lda #3dh ; set display with icon line HT9580 61 april 28, 2000 preliminary lcd_c lda #0 ; set page 0 lcd_c lda #23h ; set col0 to seg119 lcd_c lda #83h ; set gddram column address 3 lcd_c rts HT9580 62 april 28, 2000 preliminary HT9580 63 april 28, 2000 preliminary copyright 2000 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 5f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657 |
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